Summer Internship Apply Now
Internship on ASIC and Mixed-Signal VLSI Design
Duration 2 to 4 weeks Fee ₹ 499/- SPOC Mr. R Kiran Designation Assistant Professor Email summerinternships@mlritm.ac.in
Schedule Day Topic Day 1 & Day 2 VLSI Design using Cadence VLSI Overview (Analog + Digital) MOSFET Fundamentals (Analog Core) Day 3 & Day 4 CMOS Inverter (Bridge Topic) Analog Circuits – Amplifiers Day 5 & Day 6 Analog Layout + Verification Verilog Basics (Digital Start) Day 7 & Day 8 Simulation (Digital) Synthesis (RTL → Gates) Day 9 & Day 10 Timing Analysis Physical Design Day 11 & Day 12 Power + Mixed Signal Basics Final Project (Very Important)
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