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MLRITM | Top Engineering College in Hyderabad, Telangana
  • Dundigal, Hyderabad, Telangana - 500043
  • info@mlritm.ac.in

EAPCET Code: MLRS

MARRI LAXMAN REDDY

INSTITUTE OF TECHNOLOGY AND MANAGEMENT

Campus Placements 2026 :
Cognizant (72) • TVS (51) • TCS (30) • HCL (21) • Zentree Labs (9) • Deloitte (7) • Movate (7) • Intellicrats (3) • Acruent IT (2) • Aveva (1) • Juspay (1) • Work4Flow (1) • GE Appliances (1) • Mehta Hitech (1) • Terratern (1) • Innovacx (1) • Infosys (27) • ITC Infotech (13) • SLK Software (4) • Virtusa (3) • AI Health (1) • Kode Bloom (1) • PARA Innovation (1) • KT Semicon (1) • Integer Telecom (9) • JMAN (4)
Cognizant (72) • TVS (51) • TCS (30) • HCL (21) • Zentree Labs (9) • Deloitte (7) • Movate (7) • Intellicrats (3) • Acruent IT (2) • Aveva (1) • Juspay (1) • Work4Flow (1) • GE Appliances (1) • Mehta Hitech (1) • Terratern (1) • Innovacx (1) • Infosys (27) • ITC Infotech (13) • SLK Software (4) • Virtusa (3) • AI Health (1) • Kode Bloom (1) • PARA Innovation (1) • KT Semicon (1) • Integer Telecom (9) • JMAN (4)
Campus Placements 2025 :
Cognizant (65) • Global Logic (36) • Tech Mahindra (20) • Infosys (18) • CADSYS (18) • Global Quest (17) • HCL (16) • Stellar Innovation (15) • SLK (9) • Sri Chakra (8) • EIDIKO (8) • KodeBloom Technology (7) • Altus Energy (6) • Cognizant BPO (6) • Nous Infosystems (4) • Nucleonix (4) • Genpact (3) • People Tech (3)
Cognizant (65) • Global Logic (36) • Tech Mahindra (20) • Infosys (18) • CADSYS (18) • Global Quest (17) • HCL (16) • Stellar Innovation (15) • SLK (9) • Sri Chakra (8) • EIDIKO (8) • KodeBloom Technology (7) • Altus Energy (6) • Cognizant BPO (6) • Nous Infosystems (4) • Nucleonix (4) • Genpact (3) • People Tech (3)

Summer Internship

Summer Internship

Internship on ASIC and Mixed-Signal VLSI Design
Duration2 to 4 weeks
Fee₹ 499/-
SPOCMr. R Kiran
DesignationAssistant Professor
Emailsummerinternships@mlritm.ac.in

Schedule

DayTopic
Day 1 & Day 2
  • VLSI Design using Cadence VLSI Overview (Analog + Digital)
  • MOSFET Fundamentals (Analog Core)
Day 3 & Day 4
  • CMOS Inverter (Bridge Topic)
  • Analog Circuits – Amplifiers
Day 5 & Day 6
  • Analog Layout + Verification
  • Verilog Basics (Digital Start)
Day 7 & Day 8
  • Simulation (Digital)
  • Synthesis (RTL → Gates)
Day 9 & Day 10
  • Timing Analysis
  • Physical Design
Day 11 & Day 12
  • Power + Mixed Signal Basics
  • Final Project (Very Important)
Brochure